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Disambiguation of "Sechen, Carl"

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Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA.

, , , , , , , and . ACM Great Lakes Symposium on VLSI, page 171-176. ACM, (2019)

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Wolfgang Carl

Julia Carli

Hans Carlowitz

Jörg Carls

Lars-Anders Carlson

 

Other publications of authors with the same name

Clock-delayed domino for dynamic circuit design., and . IEEE Trans. Very Large Scale Integr. Syst., 8 (4): 425-430 (2000)A MEMS-Assisted Temperature Sensor With 20-µK Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 52 (1): 185-197 (2017)Timing- and crosstalk-driven area routing., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (4): 528-544 (2001)A parallel standard cell placement algorithm., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (11): 1342-1357 (1997)Mickey: a macro cell global router., and . EURO-DAC, page 248-252. EEE Computer Society, (1991)Timing and Crosstalk Driven Area Routing., , and . DAC, page 378-381. ACM Press, (1998)Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing.. DAC, page 73-80. ACM, (1988)Chip-level area routing., , and . ISPD, page 197-204. ACM, (1998)Post-synthesis leakage power minimization., and . DATE, page 99-104. IEEE, (2012)Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage., , , , and . FPT, page 291-294. IEEE, (2019)