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Disambiguation of "Jose, Anup P."

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Pulsed current-mode signaling for nearly speed-of-light intrachip communication.

, , and . IEEE J. Solid State Circuits, 41 (4): 772-780 (2006)

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Vilma Anupöld

Anup Das

Anup Pradhan

Anup Ramachandran

Anup Biswas

 

Other publications of authors with the same name

A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process., , , , , , , , and . CICC, page 1-4. IEEE, (2019)Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication., and . IEEE J. Solid State Circuits, 42 (6): 1415-1424 (2007)Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application., , , , and . ASYNC, page 216-226. IEEE Computer Society, (2003)An on-chip jitter measurement circuit with sub-picosecond resolution., , and . ESSCIRC, page 157-160. IEEE, (2005)3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 48 (11): 2582-2594 (2013)Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS., , , , , , , , , and 3 other author(s). CICC, page 1-4. IEEE, (2014)A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (8): 1932-1944 (2015)A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process., , , , , , and . IEEE J. Solid State Circuits, 57 (8): 2521-2531 (2022)Pulsed current-mode signaling for nearly speed-of-light intrachip communication., , and . IEEE J. Solid State Circuits, 41 (4): 772-780 (2006)