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Disambiguation of "Kosaka, Daisuke"

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A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design.

, , , , , , and . CICC, page 219-222. IEEE, (2009)

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Daisuke Yoshida

Daisuke Shibata

Daisuke Akimoto

Daisuke Shimizu

Daisuke Mashima

 

Other publications of authors with the same name

An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology., , , , , , and . IEICE Trans. Electron., 93-C (6): 820-826 (2010)A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design., , , , , , and . CICC, page 219-222. IEEE, (2009)Multi-axis Force Sensor Using Piezoresistors and a Plate-Like Structure., , , , , , , , and . IROS, page 563-567. IEEE, (1988)Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation., and . ASP-DAC, page 677-682. IEEE, (2006)A 6-bit arbitrary digital noise emulator in 65nm CMOS technology., , , , , , and . CICC, page 187-190. IEEE, (2009)Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (2): 380-387 (2007)Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation., , , and . CICC, page 849-852. IEEE, (2007)Chip-Level Substrate Coupling Analysis with Reference Structures for Verification., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (12): 2651-2660 (2007)Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (2): 440-447 (2010)