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A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI., , , and . VLSI-SoC, page 95-98. IEEE, (2019)Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing., , and . CoRR, (2020)Streaming architectures for extreme energy efficiency in high-performance computing.. ETH Zurich, Zürich, Switzerland, (2021)Needle in a Haystack: Limiting the Search Space in Mission-aware Packet Forwarding for Drones., , , and . SmartObjects@MobiCom, page 31-36. ACM, (2015)A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets, , , and . (2018)The Floating Point Trinity: A Multi-modal Approach to Extreme Energy-Efficiency and Performance., , , and . ICECS, page 767-770. IEEE, (2019)Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads., , , and . CoRR, (2020)Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing., , and . IEEE Micro, 41 (2): 36-42 (2021)Implementing CNN Layers on the Manticore Cluster-Based Many-Core Architecture., , and . CoRR, (2021)Design of an open-source bridge between non-coherent burst-based and coherent cache-line-based memory systems., , , and . CF, page 81-88. ACM, (2020)