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Disambiguation of "Muraoka, Michiaki"

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Synthesis for SoC architecture using VCores.

, , , , and . ASP-DAC, page 446-452. ACM, (2003)

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Michiaki Horie

 

Other publications of authors with the same name

A Partial Scan Design Method Based on n-Fold Line-up Structures., , , , and . Asian Test Symposium, page 306-. IEEE Computer Society, (1997)A DFT Selection Method for Reducing Test Application Time of System-on-Chips., , , , and . IEICE Trans. Inf. Syst., 87-D (3): 609-619 (2004)A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint., , , , and . Asian Test Symposium, page 130-135. IEEE Computer Society, (2003)A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits., , and . VTS, page 328-335. IEEE Computer Society, (2002)Logic simulation for LSI., , and . DAC, page 755-761. ACM/IEEE, (1982)A critical net reshape-router for high-performance VLSI layout design., , , and . APCCAS, page 587-590. IEEE, (2014)VCore-based platform for SoC design., , , and . ASP-DAC, page 453-458. ACM, (2003)A multilayer crosstalk avoidance router using restricted maze grids., , and . MWSCAS, page 641-644. IEEE, (2013)A SoC Test Strategy Based on a Non-Scan DFT Method., , and . Asian Test Symposium, page 305-310. IEEE Computer Society, (2002)Design methodology for SoC arthitectures based on reusable virtual cores., , , , and . ASP-DAC, page 256-262. IEEE Computer Society, (2004)