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Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.

, , , , и . ISQED, стр. 99-104. IEEE Computer Society, (2003)

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Schi-chien Tsai

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Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms., и . ISCAS, стр. 287-290. IEEE, (1994)Boolean Matching Using Generalized Reed-Muller Forms., и . DAC, стр. 339-344. ACM Press, (1994)Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D., , , , , , и . Asian Test Symposium, стр. 265-. IEEE Computer Society, (2001)On RTL scan design., , , , , , и . ITC, стр. 728-737. IEEE Computer Society, (2001)Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm., , , , , , , и . ITC, стр. 74-82. IEEE Computer Society, (2002)Logic Synthesis for Testability., и . Great Lakes Symposium on VLSI, стр. 118-121. IEEE Computer Society, (1996)Multilevel Logic Synthesis for Arithmetic Functions., и . DAC, стр. 242-247. ACM Press, (1996)Efficient minimization algorithms for fixed polarity AND/XOR canonical networks., и . Great Lakes Symposium on VLSI, стр. 76-79. IEEE, (1993)Effect of RTL coding style on testability., , , , и . CICC, стр. 255-258. IEEE, (2001)Constraint Driven Pin Mapping for Concurrent SOC Testing., , , , , , , и . ASP-DAC/VLSI Design, стр. 511-516. IEEE Computer Society, (2002)