( en | de | ru )

 

Disambiguation of "Rouzeyre, Bruno"

Author of the publication

copydeleteadd this publication to your clipboard
Alleviating DFT Cost Using Testability Driven HLS.

, , and . Asian Test Symposium, page 46-51. IEEE Computer Society, (1998)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Horst Bruno

Armin Bruno

Horst Bruno

Eugen Bruno

Axel Brunold

 

Other publications of authors with the same name

A Flip-Flop Matching Engine to Verify Sequential Optimizations., , and . Comput. Artif. Intell., 23 (5): 437-460 (2004)On Preventing SAT Attack with Decoy Key-Inputs., , , and . ISVLSI, page 114-119. IEEE, (2021)High-level synthesis for easy testability., , and . ED&TC, page 198-206. IEEE Computer Society, (1995)Analyzing testability from behavioral to RT level., , and . ED&TC, page 158-165. IEEE Computer Society, (1997)Laser attacks on integrated circuits: From CMOS to FD-SOI., , , , , , , , , and . DTIS, page 1-6. IEEE, (2014)A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans., , , , and . IOLTS, page 49-54. IEEE, (2014)Compression-based SoC Test Infrastructures., , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-15. Springer, (2007)Scan chain encryption for the test, diagnosis and debug of secure circuits., , , , , and . ETS, page 1-6. IEEE, (2017)An Integrated Validation Environment for Differential Power Analysis., , and . DELTA, page 527-532. IEEE Computer Society, (2008)Built-in self-test for manufacturing TSV defects before bonding., , , and . VTS, page 1-6. IEEE Computer Society, (2014)