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O for on-chip signaling in 45nm CMOS SOI.

Y. Liu, P. Hsieh, S. Kim, J. sun Seo, R. Montoye, L. Chang, J. Tierno, and D. Friedman. ISSCC, page 400-401. IEEE, (2013)

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Humberto Jorge José

Pietro Tierno

Nadine José Gonzalez

Jose A C Broekaert

José Navarrete

Other publications of authors with the same name

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.A. Rylyakov, J. Tierno, H. Ainspan, J. Plouchart, J. Bulzacchelli, Z. Deniz, and D. Friedman. ISSCC, page 94-95. IEEE, (2009)Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology.Z. Deng, S. Whiteley, T. Duzer, and J. Tierno. ASYNC, page 274-. IEEE Computer Society, (1998)Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J. Plouchart, B. Sadhu, B. Parker and 4 other author(s). CICC, page 1-4. IEEE, (2013)A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.Y. Liu, P. Hsieh, S. Kim, J. sun Seo, R. Montoye, L. Chang, J. Tierno, and D. Friedman. ISSCC, page 400-401. IEEE, (2013)A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.S. Asaad, R. Bellofatto, B. Brezzo, C. Haymes, M. Kapur, B. Parker, T. Roewer, P. Saha, T. Takken, and J. Tierno. FPGA, page 153-162. ACM, (2012)A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS.A. Agrawal, J. Bulzacchelli, T. Dickson, Y. Liu, J. Tierno, and D. Friedman. IEEE J. Solid State Circuits, 47 (12): 3220-3231 (2012)Integrated transversal equalizers in high-speed fiber-optic systems.H. Wu, J. Tierno, P. Pepeljugoski, J. Schaub, S. Gowda, J. Kash, and A. Hajimiri. IEEE J. Solid State Circuits, 38 (12): 2131-2137 (2003)A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS.A. Rylyakov, J. Tierno, D. Turker, J. Plouchart, H. Ainspan, and D. Friedman. ISSCC, page 516-517. IEEE, (2008)Low-energy asynchronous memory design.J. Tierno, and A. Martin. ASYNC, page 176-185. IEEE, (1994)A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS.J. Plouchart, M. Sanduleanu, Z. Deniz, T. Beukema, S. Reynolds, B. Parker, M. Beakes, J. Tierno, and D. Friedman. CICC, page 1-4. IEEE, (2012)

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Disambiguation of "Tierno, José A."

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A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.

Please choose a person to relate this publication to

Humberto Jorge José

Pietro Tierno

Nadine José Gonzalez

Jose A C Broekaert

José Navarrete

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tierno, José A."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.

Please choose a person to relate this publication to

Humberto Jorge José

Pietro Tierno

Nadine José Gonzalez

Jose A C Broekaert

José Navarrete

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.