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Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs.

H. Morishita, Y. Osana, N. Fujita, and H. Amano. FPT, page 193-200. IEEE, (2008)

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FPL Demo: Kyokko - An Aurora 64b66b compatible 100 Gbps Communication Controller.A. Tomori, and Y. Osana. FPL, page 472. IEEE, (2022)A Framework for Implementing a Network-Based Stochastic Biochemical Simulator on an FPGA.M. Yoshimi, Y. Nishikawa, T. Kojima, Y. Osana, A. Funahashi, N. Hiroi, Y. Shibata, H. Yamada, H. Kitano, and H. Amano. FPT, page 193-200. IEEE, (2007)An SDR implementation of HF ocean radar on FPGA SoC.Y. Osana, and S. Fujii. ICCE, page 1-3. IEEE, (2024)A 100Gbps-ready Low Latency on-Chip Router for FPGA clusters.Y. Tani, and Y. Osana. ICCE, page 1-3. IEEE, (2024)A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA.H. Yamada, Y. Osana, T. Ishimori, T. Ooya, M. Yoshimi, Y. Nishikawa, A. Funahashi, N. Hiroi, H. Amano, Y. Shibata and 1 other author(s). ReConFig, page 125-130. IEEE Computer Society, (2009)Enhanced Fair Joint Multiple Resource Allocation Method in All-IP Networks.Y. Osana, and S. ichi Kuribayashi. AINA Workshops, page 163-168. IEEE Computer Society, (2010)Accurate identification of orthologous segments among multiple genomes.T. Hachiya, Y. Osana, K. Popendorf, and Y. Sakakibara. Bioinform., 25 (11): 1474 (2009)A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA.Y. Osana, Y. Iwaoka, T. Fukushima, M. Yoshimi, A. Funahashi, N. Hiroi, Y. Shibata, N. Iwanaga, H. Kitano, and H. Amano. FPL, page 574-577. IEEE, (2005)Dynamically reconfigurable flux limiter functions in MUSCL scheme.M. Talip, T. Akamine, Y. Osana, N. Fujita, and H. Amano. ReCoSoC, page 1-7. IEEE, (2012)Evaluation of Congestion Control Methods for Joint Multiple Resource Allocation.T. Yoshino, Y. Osana, and S. ichi Kuribayashi. NBiS, page 94-97. IEEE Computer Society, (2010)

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Disambiguation of "Osana, Yasunori"

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Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs.

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Disambiguation of "Osana, Yasunori"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs.

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Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs.