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Hybrid-comp: A criticality-aware compressed last-level cache.

, , , и . ISQED, стр. 25-30. IEEE, (2018)

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Tayebeh Jadidi

Yasser Jadidi

Amir Jadidi

Naghi Jadidi

Mohammed-Ali Amin

 

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High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement., , и . ISLPED, стр. 79-84. IEEE/ACM, (2011)A morphable phase change memory architecture considering frequent zero values., , , и . ICCD, стр. 373-380. IEEE Computer Society, (2011)Hybrid-comp: A criticality-aware compressed last-level cache., , , и . ISQED, стр. 25-30. IEEE, (2018)Optimizing energy consumption in GPUS through feedback-driven CTA scheduling., , , и . SpringSim (HPC), стр. 12:1-12:12. ACM, (2017)Selective Caching: Avoiding Performance Valleys in Massively Parallel Architectures., , и . PDP, стр. 290-298. IEEE, (2020)Leveraging value locality for efficient design of a hybrid cache in multicore processors., , , и . ICCAD, стр. 1-8. IEEE, (2017)MLC PCM main memory with accelerated read., , , , и . ISPASS, стр. 143-144. IEEE Computer Society, (2016)Performance and Power-Efficient Design of Dense Non-Volatile Cache in CMPs., , , и . IEEE Trans. Computers, 67 (7): 1054-1061 (2018)HL-PCM: MLC PCM Main Memory with Accelerated Read., , , , и . IEEE Trans. Parallel Distributed Syst., 28 (11): 3188-3200 (2017)Exploring the Potential for Collaborative Data Compression and Hard-Error Tolerance in PCM Memories., , , , , и . DSN, стр. 85-96. IEEE Computer Society, (2017)