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Hybrid on-line self-test architecture for computational units on embedded processor cores.

, , , and . DDECS, page 1-6. IEEE, (2019)

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A Suitability Analysis of Software Based Testing Strategies for the On-line Testing of Artificial Neural Networks Applications in Embedded Devices., , , and . IOLTS, page 1-6. IEEE, (2021)New categories of Safe Faults in a processor-based Embedded System., , , , , , and . CoRR, (2020)Assessing Test Procedure Effectiveness for Power Devices., and . DCIS, page 1-6. IEEE, (2018)Non-Intrusive Self-Test Library for Automotive Critical Applications: Constraints and Solutions., , , , , , , , and . DATE, page 920-923. IEEE, (2019)Hybrid on-line self-test architecture for computational units on embedded processor cores., , , and . DDECS, page 1-6. IEEE, (2019)Parallel software-based self-test suite for multi-core system-on-chip: Migration from single-core to multi-core automotive microcontrollers., , , , and . DTIS, page 1-6. IEEE, (2018)Software-based self-test techniques of computational modules in dual issue embedded processors., , , , , , , and . ETS, page 1-2. IEEE, (2015)Deterministic Cache-based Execution of On-line Self-Test Routines in Multi-core Automotive System-on-Chips., , , , , , , and . DATE, page 1235-1240. IEEE, (2020)Facilitating Fault-Simulation Comprehension through a Fault-Lists Analysis Tool., , and . LASCAS, page 77-80. IEEE, (2019)In-field functional test programs development flow for embedded FPUs., , , , and . DFT, page 107-110. IEEE Computer Society, (2016)