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Piece Matching Optimization Based on Improved Genetic Strategy.

, , and . ICAIP, page 138-142. ACM, (2020)

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Generating the highest power with a tiny and distant inductively coupled coil., and . ISIE, page 477-480. IEEE, (2016)A high resolution capacitance deviation-to-digital converter utilizing time stretching., , , , and . SoCC, page 83-86. IEEE, (2009)A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines., , , and . SoCC, page 43-46. IEEE, (2009)High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line., , , , , , , and . ESSCIRC, page 311-314. IEEE, (2013)Highest Wireless Power: Inductively Coupled Or RF?, and . ISQED, page 298-301. IEEE, (2020)Highest Maximum Power Point of Radially Distant Inductively Coupled Power Receivers With Deep Submicron CMOS., and . IEEE Trans. Ind. Informatics, 16 (2): 1086-1093 (2020)Clock Ensemble Algorithm Test in the Establishment of Space-Based Time Reference., , , and . Remote. Sens., 15 (5): 1227 (March 2023)A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (3): 169-173 (2011)A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter., , , , , , , , and . ISSCC, page 254-255. IEEE, (2013)A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications., , , , , , , , and . ISSCC, page 240-242. IEEE, (2012)