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Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC.

, , , , , , and . IEEE J. Solid State Circuits, 45 (4): 719-730 (2010)

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A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers., , , , , and . VLSIC, page 32-33. IEEE, (2012)A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer., , , , , , and . CICC, page 1-4. IEEE, (2010)Binary Access Memory: An optimized lookup table for successive approximation applications., , , , and . ISCAS, page 1620-1623. IEEE, (2011)A 76- to 81-GHz Multi-Channel Radar Transceiver., , , , , , and . IEEE J. Solid State Circuits, 52 (9): 2226-2241 (2017)A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application., , , , , , and . CICC, page 1-4. IEEE, (2011)A fine-grain, current mode scheme for VLSI proximity search engine., and . ICCD, page 184-185. IEEE Computer Society, (1998)A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR., , , , , , and . ISSCC, page 494-495. IEEE, (2008)Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC., , , , , , and . IEEE J. Solid State Circuits, 45 (4): 719-730 (2010)Ring amplifiers for switched-capacitor circuits., , , , , and . ISSCC, page 460-462. IEEE, (2012)