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Disambiguation of "Doblas, Max"

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Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices.

, , , , , , and . HPCA, page 1085-1098. IEEE, (2023)

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Petru Joan Maxim

Bernhard Maxeiner

Helmut Maxeiner

Hugh Maxwell

Ludger Maxrath

 

Other publications of authors with the same name

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology., , , , , , , , , and 38 other author(s). DCIS, page 1-6. IEEE, (2023)DVINO: A RISC-V Vector Processor Implemented in 65nm Technology., , , , , , , , , and 33 other author(s). DCIS, page 1-6. IEEE, (2022)WFA-GPU: gap-affine pairwise read-alignment using GPUs., , , , , , and . Bioinform., (December 2023)Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI., , , , , , , , , and . DSD, page 254-261. IEEE, (2022)GMX: Instruction Set Extensions for Fast, Scalable, and Efficient Genome Sequence Alignment., , , , , , , and . MICRO, page 1466-1480. ACM, (2023)WFAsic: A High-Performance ASIC Accelerator for DNA Sequence Alignment on a RISC-V SoC., , , , , , , and . ICPP, page 392-401. ACM, (2023)Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices., , , , , , and . HPCA, page 1085-1098. IEEE, (2023)An Academic RISC-V Silicon Implementation Based on Open-Source Components., , , , , , , , , and 24 other author(s). DCIS, page 1-6. IEEE, (2020)