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A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.

J. Miyakoshi, Y. Murachi, T. Ishihara, H. Kawaguchi, and M. Yoshimoto. IEICE Trans. Electron., 89-C (11): 1629-1636 (2006)

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Junichi Nonaka

Junichi Suzuki

Junichi Kumada

Junichi Yoshida

Other publications of authors with the same name

Size-adaptive hepatocellular carcinoma detection from 3D CT images based on the level set method.S. Yui, J. Miyakoshi, K. Matsuzaki, T. Irie, and R. Kurazume. Medical Imaging: Computer-Aided Diagnosis, volume 8315 of SPIE Proceedings, page 83151P. SPIE, (2012)An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm.M. Miyama, O. Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, J. Miyakoshi, K. Hashimoto, S. Komatsu, M. Yagi and 3 other author(s). CICC, page 167-170. IEEE, (2002)False-positive reduction of liver tumor detection using ensemble learning method.A. Miyamoto, J. Miyakoshi, K. Matsuzaki, and T. Irie. Medical Imaging: Image Processing, volume 8669 of SPIE Proceedings, page 86693B. SPIE, (2013)A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition.Y. Murachi, Y. Fukuyama, R. Yamamoto, J. Miyakoshi, H. Kawaguchi, H. Ishihara, M. Miyama, Y. Matsuda, and M. Yoshimoto. IEICE Trans. Electron., 91-C (4): 457-464 (2008)A sub-mW MPEG-4 motion estimation processor core for mobile video application.J. Miyakoshi, Y. Kuroda, M. Miyama, K. Imamura, H. Hashimoto, and M. Yoshimoto. CICC, page 181-184. IEEE, (2003)An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding.K. Mizuno, J. Miyakoshi, Y. Murachi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, H. Kawaguchi, and M. Yoshimoto. ICECS, page 1179-1182. IEEE, (2008)A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.J. Miyakoshi, Y. Murachi, M. Hamamoto, T. Iinuma, T. Ishihara, H. Kawaguchi, M. Yoshimoto, and T. Matsuno. VLSI-SoC, page 192-197. IEEE, (2006)A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.J. Miyakoshi, Y. Murachi, T. Ishihara, H. Kawaguchi, and M. Yoshimoto. IEICE Trans. Electron., 89-C (11): 1629-1636 (2006)A sub-mW MPEG-4 motion estimation processor core for mobile video application.Y. Kuroda, J. Miyakoshi, M. Miyama, K. Imamura, H. Hashimoto, and M. Yoshimoto. ASP-DAC, page 527-528. IEEE Computer Society, (2004)Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.H. Fujiwara, K. Nii, H. Noguchi, J. Miyakoshi, Y. Murachi, Y. Morita, H. Kawaguchi, and M. Yoshimoto. IEEE Trans. Very Large Scale Integr. Syst., 16 (6): 620-627 (2008)

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Disambiguation of "Miyakoshi, Junichi"

Please choose a person to relate this publication to

Junichi Nonaka

Junichi Suzuki

Junichi Kumada

Junichi Yoshida

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Miyakoshi, Junichi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.

Please choose a person to relate this publication to

Junichi Nonaka

Junichi Suzuki

Junichi Kumada

Junichi Yoshida

Other publications of authors with the same name

Disambiguation