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A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.

J. Miyakoshi, Y. Murachi, T. Ishihara, H. Kawaguchi, and M. Yoshimoto. IEICE Trans. Electron., 89-C (11): 1629-1636 (2006)

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Yuichiro Honda

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Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.H. Fujiwara, K. Nii, H. Noguchi, J. Miyakoshi, Y. Murachi, Y. Morita, H. Kawaguchi, and M. Yoshimoto. IEEE Trans. Very Large Scale Integr. Syst., 16 (6): 620-627 (2008)A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition.Y. Murachi, Y. Fukuyama, R. Yamamoto, J. Miyakoshi, H. Kawaguchi, H. Ishihara, M. Miyama, Y. Matsuda, and M. Yoshimoto. IEICE Trans. Electron., 91-C (4): 457-464 (2008)An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding.K. Mizuno, J. Miyakoshi, Y. Murachi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, H. Kawaguchi, and M. Yoshimoto. ICECS, page 1179-1182. IEEE, (2008)A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.J. Miyakoshi, Y. Murachi, T. Ishihara, H. Kawaguchi, and M. Yoshimoto. IEICE Trans. Electron., 89-C (11): 1629-1636 (2006)A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.J. Miyakoshi, Y. Murachi, M. Hamamoto, T. Iinuma, T. Ishihara, H. Kawaguchi, M. Yoshimoto, and T. Matsuno. VLSI-SoC, page 192-197. IEEE, (2006)A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation.J. Miyakoshi, Y. Murachi, K. Hamano, T. Matsuno, M. Miyama, and M. Yoshimoto. IEICE Trans. Electron., 88-C (4): 559-569 (2005)A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding.Y. Murachi, K. Mizuno, J. Miyakoshi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, T. Kamino, H. Kawaguchi and 1 other author(s). ISCAS, page 848-851. IEEE, (2008)A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.H. Fujiwara, K. Nii, J. Miyakoshi, Y. Murachi, Y. Morita, H. Kawaguchi, and M. Yoshimoto. ISLPED, page 61-66. ACM, (2006)

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Disambiguation of "Murachi, Yuichiro"

Please choose a person to relate this publication to

Yuichiro Honda

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BibSonomy

Disambiguation of "Murachi, Yuichiro"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.

Please choose a person to relate this publication to

Yuichiro Honda

Other publications of authors with the same name

Disambiguation