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Disambiguation of "Iyer, Subramanian S."

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An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT).

, , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1811-1819 (2019)

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Balasubramaniam Iyer

Preeti Ramesh Iyer

Balasubramaniam Iyer

Chandrasekhar Iyer

Pallavi Subramanian

 

Other publications of authors with the same name

Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM., , , , , and . VLSIC, page 146-147. IEEE, (2012)Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines., , , , and . CoRR, (2020)Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems., , and . IBM J. Res. Dev., 63 (6): 5:1-5:16 (2019)A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 406-407. IEEE, (2008)80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 53 (3): 949-960 (2018)Integrated neural interfaces., , , , , , , , and . MWSCAS, page 1045-1048. IEEE, (2017)45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications., , , , , , , , , and 10 other author(s). IBM J. Res. Dev., 55 (3): 5 (2011)A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration., , , and . ISSCC, page 52-54. IEEE, (2022)A Case for Packageless Processors., , , , , and . HPCA, page 466-479. IEEE Computer Society, (2018)1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 35 (11): 1673-1679 (2000)