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Disambiguation of "Kirihata, Toshiaki"

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A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS.

, , , , , , , , , , and . ISSCC, page 406-407. IEEE, (2008)

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An 800-MHz embedded DRAM with a concurrent refresh mode., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 40 (6): 1377-1387 (2005)A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 33 (11): 1711-1719 (1998)Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM., , , , , , and . IEEE J. Solid State Circuits, 48 (4): 940-947 (2013)A low-noise TTL-compatible CMOS off-chip driver circuit., , , and . IBM J. Res. Dev., 39 (1-2): 105-112 (1995)An on-chip dual supply charge pump system for 45nm PD SOI eDRAM., , , , , , , , , and 3 other author(s). ESSCIRC, page 66-69. IEEE, (2008)Three Dimensional integration - Considerations for memory applications., , and . CICC, page 1-7. IEEE, (2011)Advanced memory topics., and . CICC, page 1. IEEE, (2014)A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM., , , , , and . IEEE J. Solid State Circuits, 48 (11): 2934-2943 (2013)A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity., , , , , , , , , and 4 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)