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Overview of low-power wake-up radio design insights.. CICC, стр. 1-59. IEEE, (2018)A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET., , , , и . VLSI Circuits, стр. 23-24. IEEE, (2018)A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS., , , и . A-SSCC, стр. 1-4. IEEE, (2015)An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS., , , , , и . VLSIC, стр. 1-2. IEEE, (2014)A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS., , , , , , , , , и 5 other автор(ы). VLSIC, стр. 76-77. IEEE, (2012)32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver., , , , , , , , , и 13 other автор(ы). ISSCC, стр. 62-64. IEEE, (2012)A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN., , , , , , , и . CICC, стр. 1-4. IEEE, (2014)A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS., , , и . ISSCC, стр. 76-77. IEEE, (2009)