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Disambiguation of "Kim, Yunsaing"

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A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX.

, , , , , , and . ISSCC, page 308-309. IEEE, (2013)

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Ky ng Kim

Die Artikelstruktur in passiven zweisprachigen Wörterbüchern Deutsch-Koreanisch: Konzeption zur Erstellung eines zweisprachigen Lernerwörterbuchs Deutsch-Koreanisch. Uni Heidelberg, (2008)

Bongcheol Kim

Youngsang Kim

Sunghun Kim

Taekwan Kim

 

Other publications of authors with the same name

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX., , , , , , and . ISSCC, page 308-309. IEEE, (2013)A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture., , , , , , , , , and 12 other author(s). ISSCC, page 40-41. IEEE, (2012)An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface., , , , , , , and . ISSCC, page 312-313. IEEE, (2013)A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface., , , , , , , , , and 1 other author(s). ISSCC, page 48-50. IEEE, (2012)Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC., , , , , , , , , and 1 other author(s). 3DIC, page TS8.25.1-TS8.25.5. IEEE, (2015)A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications., , , , , , , , , and 2 other author(s). VLSIC, page 184-. IEEE, (2015)An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface., , , , , , , , and . IEEE J. Solid State Circuits, 49 (11): 2618-2630 (2014)25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector., , , , , , , , , and 13 other author(s). ISSCC, page 434-435. IEEE, (2014)