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F3: Emerging technologies for wireline communication., , , , , , и . ISSCC, стр. 504-505. IEEE, (2013)F5: Advanced optical communication: From devices, circuits, and architectures to algorithms., , , , , и . ISSCC, стр. 514-516. IEEE, (2018)A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS., , и . IEEE J. Solid State Circuits, 56 (3): 750-762 (2021)A Wideband Injection Locked Quadrature Clock Generation and Distribution Technique for an Energy-Proportional 16-32 Gb/s Optical Receiver in 28 nm FDSOI CMOS., , и . IEEE J. Solid State Circuits, 51 (10): 2446-2462 (2016)A 2.4pJ/b 100Gb/s 3D-integrated PAM-4 Optical Transmitter with Segmented SiP MOSCAP Modulators and a 2-Channel 28nm CMOS Driver., , , , , , , и . ISSCC, стр. 284-286. IEEE, (2022)A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS., , , , , , , , , и . CICC, стр. 1-2. IEEE, (2021)A 41.2 nJ/class, 32-Channel On-Chip Classifier for Epileptic Seizure Detection., , , , и . EMBC, стр. 3693-3696. IEEE, (2018)Decoding Kinematics from Human Parietal Cortex using Neural Networks., , , , , , , , и . NER, стр. 1138-1141. IEEE, (2019)A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 57 (9): 2752-2763 (2022)A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS., , и . IEEE J. Solid State Circuits, 51 (8): 1734-1743 (2016)