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Disambiguation of "Leblebici, Yusuf"

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A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS.

, , , , , , , , , and . CICC, page 1-2. IEEE, (2021)

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Yusuf

Erhan Leblebici

Nigem Yusuf

Faisal Yusuf

Sherif Yusuf

 

Other publications of authors with the same name

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 339-351 (2016)A low-power, multichannel gated oscillator-based CDR for short-haul applications., , , and . ISLPED, page 107-110. ACM, (2005)Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library., , , , , and . DAC, page 1014-1019. ACM, (2011)Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors., , , and . DAC, page 42-47. ACM, (2012)Self-Calibrated Delay-Based LSB Extraction for Resolution Improvement in SAR ADCs., , and . NORCAS, page 1-7. IEEE, (2019)Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link., , , , and . MWSCAS, page 1147-1150. IEEE, (2019)Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique., , and . 3DIC, page 1-5. IEEE, (2016)A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories., , , and . ASP-DAC, page 835-840. IEEE, (2009)Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology., , , and . NORCAS, page 1-4. IEEE, (2015)Non-filamentary non-volatile memory elements as synapses in neuromorphic systems., , , , , , , , , and . NVMTS, page 1-6. IEEE, (2019)