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Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors., , , and . IJHPCN, 1 (1/2/3): 4-16 (2004)Performance optimization of multiple memory architectures for DSP., , and . ISCAS (5), page 469-472. IEEE, (2002)An Integrated Framework of Design Optimization and Space Minimization for DSP applications., , and . ISCAS (5), page 601-604. IEEE, (2003)Loop scheduling with timing and switching-activity minimization for VLIW DSP., , , , and . ACM Trans. Design Autom. Electr. Syst., 11 (1): 165-185 (2006)Towards the design of efficient hash-based indexing scheme for growing databases on non-volatile memory., , , , , and . Future Gener. Comput. Syst., (2020)Algorithms for Optimally Arranging Multicore Memory Structures., , , , and . EURASIP J. Embed. Syst., (2010)Data Placement and Duplication for Embedded Multicore Systems With Scratch Pad Memory., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (6): 809-817 (2013)Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (10): 1450-1462 (2014)Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors., , , , and . ACM Trans. Embed. Comput. Syst., 13 (4): 79:1-79:25 (2014)Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs., , , , , and . EUC, volume 3824 of Lecture Notes in Computer Science, page 121-130. Springer, (2005)