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Collective Test Generation and Test Set Compaction., and . ISCAS, page 2008-2011. IEEE, (1995)Mixed signal verification to avoid integration mismatch in complex SoCs., , and . LATS, page 1-6. IEEE, (2017)Exploring the problems of placement and mapping in NoC-based reconfizurable systems., and . ReConFig, page 1-4. IEEE, (2013)Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions., , and . IDT, page 1-6. IEEE, (2013)DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost., , , and . ARC, volume 9040 of Lecture Notes in Computer Science, page 419-426. Springer, (2015)Formally verifying an RTOS scheduling monitor IP core in embedded systems., , , and . LATW, page 1-6. IEEE, (2011)BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units., , , and . LATW, page 64-69. IEEE, (2002)Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation., , and . SoCC, page 41-46. IEEE, (2016)On TLM traffic accuracy: A multifractal perspective., and . LASCAS, page 1-4. IEEE, (2018)The LRD traffic impact on the NoC-based SoCs., , , and . SBCCI, page 97-102. ACM, (2010)