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Disambiguation of "Yu, Zhiyi"

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A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations.

, , , , , and . IEICE Electron. Express, 20 (11): 20230152 (2023)

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Zhiyi Ding

Zhiyi Lv

Yu-Ting Yu

Yu-Yu Su

Sze-Man Yu

Metal complexes with enolatoimine ligands for controlled olefin polymerizations. Uni Konstanz, (2009)
 

Other publications of authors with the same name

A 2D mesh NoC with self-configurable and shared-FIFOs routers., , , , and . ASICON, page 1-4. IEEE, (2013)A fast multi-core virtual platform and its application on software development., , , , and . ASICON, page 1-4. IEEE, (2013)A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array., , , , , , , , , and 4 other author(s). ISSCC, page 56-57. IEEE, (2013)A low power register file with asynchronously controlled read-isolation and software-directed write-discarding., , , , and . ISCAS, page 349-352. IEEE, (2013)A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer., , , , , and . CICC, page 1-4. IEEE, (2015)High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors., and . IEEE Trans. Very Large Scale Integr. Syst., 17 (1): 66-79 (2009)Architecture and Evaluation of an Asynchronous Array of Simple Processors., , , , , , , , and . J. Signal Process. Syst., 53 (3): 243-259 (2008)A Shared Memory Module for Asynchronous Arrays of Processors., , and . EURASIP J. Embed. Syst., (2007)Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (5): 963-970 (2013)NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (9): 1966-1978 (2020)