( en | de | ru )

 

Disambiguation of "Lanuzza, Marco"

Author of the publication

copydeleteadd this publication to your clipboard
Dynamic gate-level body biasing for subthreshold digital design.

, , and . LASCAS, page 1-4. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Johannes Marcour

Monika Marcotty

Hans-Ernst Marcolin

Carlos Javier Marcos Navas

Massimiliano Marcon

 

Other publications of authors with the same name

Low bit rate image compression core for onboard space applications., , , , and . IEEE Trans. Circuits Syst. Video Techn., 16 (1): 114-128 (2006)Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory., , , and . ICECS, page 123-124. IEEE, (2019)An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops., , , and . ICECS, page 158-161. IEEE, (2019)AIDA: Associative In-Memory Deep Learning Accelerator., , , and . IEEE Micro, 42 (6): 67-75 (2022)Double-precision Dual Mode Logic carry-save multiplier., , and . Integr., (2019)Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW., , , , , and . IEEE J. Solid State Circuits, 56 (10): 3134-3144 (2021)Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach., , , , and . IEEE Access, (2023)FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture., , , , and . IEEE Access, (2024)Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing., , , , , and . CoRR, (2022)Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications., , and . ISLPED, page 161-166. ACM, (2005)