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Disambiguation of "Taco, Ramiro"

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Dynamic gate-level body biasing for subthreshold digital design.

, , and . LASCAS, page 1-4. IEEE, (2014)

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Taco Kuiper

Theofanis Tacou

Ramiro Brenes

Ramiro Alberio

Ramiro Medina

 

Other publications of authors with the same name

Dynamic gate-level body biasing for subthreshold digital design., , and . LASCAS, page 1-4. IEEE, (2014)Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow., , , , and . IEEE Access, (2023)Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells., , , , , and . LASCAS, page 1-4. IEEE, (2022)A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic., , , , , and . IEEE J. Solid State Circuits, 57 (2): 596-608 (2022)Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology., , , and . ISCAS, page 41-44. IEEE, (2016)High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator., , , , and . LASCAS, page 1-4. IEEE, (2021)RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies., , , , , , and . LASCAS, page 1-4. IEEE, (2021)Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths., , , , and . ISCAS, page 1. IEEE, (2021)An 88-fJ/40-MHz 0.4 V-0.61-pJ/1-GHz 0.9 V Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI., , , and . IEEE J. Solid State Circuits, 54 (2): 560-568 (2019)Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines., , , and . Int. J. Circuit Theory Appl., 43 (11): 1523-1540 (2015)