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Disambiguation of "Timarchi, Somayeh"

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Area-Time-Efficient Scalable Schoolbook Polynomial Multiplier for Lattice-Based Cryptography.

, , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (12): 5079-5083 (2022)

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Somayeh Taheri

Somayeh Abdi

Somayeh Haidary

Somayeh Mohammad-Khani

 

Other publications of authors with the same name

Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling., and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (6): 2236-2240 (June 2023)Fast architecture for decimal digit multiplication., , , and . Microprocess. Microsystems, 39 (4-5): 296-301 (2015)High-speed energy-efficient 5: 2 compressor., , and . MIPRO, page 80-84. IEEE, (2014)A unified addition structure for moduli set 2n-1, 2n, 2n+1 based on a novel RNS representation., , and . ICCD, page 247-252. IEEE Computer Society, (2010)Optimized Parity-Based Error Detection and Correction Methods for Residue Number System., , and . Journal of Circuits, Systems, and Computers, 28 (1): 1950002:1-1950002:15 (2019)Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix., , and . Microelectron. J., (2019)Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (4): 1649-1659 (April 2023)Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (3): 1259-1268 (2021)Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization., , and . Microprocess. Microsystems, (September 2022)Efficient Reverse Converter Designs for the New 4-Moduli Sets 2n -1, 2n, 2n +1, 22n + 1-1 and 2n -1, 2n +1, 22n, 22n +1 Based on New CRTs., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (4): 823-835 (2010)