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A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.

Z. Zhang, X. Shen, Y. Li, G. Li, N. Qi, J. Liu, N. Wu, L. Liu, Y. Chen, and Z. Zhang. APCCAS, page 556-559. IEEE, (2022)

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Liu Liu

Liyuan Wang-Scheerer

Keetsin Liu

Other publications of authors with the same name

Defend the Clique-based Attack for Data Privacy.M. Han, D. Miao, J. Wang, and L. Liu. COCOA, volume 11346 of Lecture Notes in Computer Science, page 262-280. Springer, (2018)Contrast Subgraph Mining from Coherent Cores.J. Shang, X. Shi, M. Jiang, L. Liu, T. Hanratty, and J. Han. CoRR, (2018)A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits.J. Yang, Z. Zhang, N. Qi, L. Liu, J. Liu, and N. Wu. Sci. China Inf. Sci., 62 (6): 62405:1-62405:16 (2019)A Discrete-Time Audio ΔΣ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques.S. Ma, L. Liu, T. Fang, J. Liu, and N. Wu. IEEE J. Solid State Circuits, 55 (2): 333-343 (2020)Expert Finding in Heterogeneous Bibliographic Networks with Locally-trained Embeddings.H. Gui, Q. Zhu, L. Liu, A. Zhang, and J. Han. CoRR, (2018)CompSNN: A lightweight spiking neural network based on spatiotemporally compressive spike features.T. Wang, C. Shi, X. Zhou, Y. Lin, J. He, P. Gan, P. Li, Y. Wang, L. Liu, N. Wu and 1 other author(s). Neurocomputing, (2021)A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR.Q. Liao, Y. Zhang, S. Ma, L. Wang, L. Li, G. Li, Z. Zhang, J. Liu, N. Wu, L. Liu and 3 other author(s). IEEE J. Solid State Circuits, 57 (3): 767-780 (2022)A2Text-Net: A Novel Deep Neural Network for Sarcasm Detection.L. Liu, J. Priestley, Y. Zhou, H. Ray, and M. Han. CogMI, page 118-126. IEEE, (2019)High-speed visual target tracking with mixed rotation invariant description and skipping searching.Y. Yang, J. Yang, Z. Zhang, L. Liu, and N. Wu. Sci. China Inf. Sci., 60 (6): 62401 (2017)High-speed target tracking system based on multi-interconnection heterogeneous processor and multi-descriptor algorithm.J. Wang, Y. Yang, L. Liu, and N. Wu. Sci. China Inf. Sci., 62 (6): 69401:1-69401:3 (2019)

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Disambiguation of "Liu, Liyuan"

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A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Liyuan Wang-Scheerer

Keetsin Liu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Liu, Liyuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Liyuan Wang-Scheerer

Keetsin Liu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.