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Disambiguation of "Chattopadhyay, Anupam"

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Towards Designing a Secure RISC-V System-on-Chip: ITUS.

, , , , , , and . J. Hardw. Syst. Secur., 4 (4): 329-342 (2020)

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Anupam Chattopadhyay

Anupam Singh

Anupam Karmakar

Anupam Sengupta

Dhrupadi Chattopadhyay

 

Other publications of authors with the same name

Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays., , and . VLSI-SoC, page 1-6. IEEE, (2016)SI-DFA: Sub-expression integrated Deterministic Finite Automata for Deep Packet Inspection., , and . HPSR, page 164-170. IEEE, (2013)Design and analysis of layered coarse-grained reconfigurable architecture., , and . ReConFig, page 1-6. IEEE, (2012)Crack me if you can: hardware acceleration bridging the gap between practical and theoretical cryptanalysis?: a Survey., , , and . SAMOS, page 167-172. ACM, (2018)Cryptanalysis of the Double-Feedback XOR-Chain Scheme Proposed in Indocrypt 2013., , and . INDOCRYPT, volume 8885 of Lecture Notes in Computer Science, page 179-196. Springer, (2014)Trace Buffer Attack: Security versus observability study in post-silicon debug., , and . VLSI-SoC, page 355-360. IEEE, (2015)Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies., , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (11): 2469-2472 (2019)Accelerating Binary-Matrix Multiplication on FPGA., , and . SoCC, page 254-259. IEEE, (2019)Complexity Analysis of Reversible Logic Synthesis., , and . CoRR, (2014)System-level reliability exploration framework for heterogeneous MPSoC., , , and . ACM Great Lakes Symposium on VLSI, page 9-14. ACM, (2014)