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Disambiguation of "Kumar, Vinay B. Y."

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Towards Designing a Secure RISC-V System-on-Chip: ITUS.

, , , , , , and . J. Hardw. Syst. Secur., 4 (4): 329-342 (2020)

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Vinay Kumar

Vinay Kumar Aggarwal

Vinay Suryaprakash

Vinay Bettadapura

Vinay Vijayakumar

 

Other publications of authors with the same name

Towards Designing a Secure RISC-V System-on-Chip: ITUS., , , , , , and . J. Hardw. Syst. Secur., 4 (4): 329-342 (2020)Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks., , , , and . DATE, page 561-564. IEEE, (2021)FPGA-based implementation of M4RM for matrix multiplication over GF(2)., , and . VDAT, page 1-2. IEEE, (2014)Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems., , , and . VLSI-DAT, page 1-4. IEEE, (2014)A Novel Duplication Based Countermeasure to Statistical Ineffective Fault Analysis., , , , , and . ACISP, volume 12248 of Lecture Notes in Computer Science, page 525-542. Springer, (2020)Recruiting Fault Tolerance Techniques for Microprocessor Security., , , , , and . ATS, page 80-85. IEEE, (2019)AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 508-521 (2022)Relaxation Based Circuit Simulation Acceleration over CPU-FPGA., , , , , and . VLSID, page 409-414. IEEE Computer Society, (2016)Lightweight Forth Programmable NoCs., , , and . VLSID, page 368-373. IEEE Computer Society, (2018)Secure Your SoC: Building System-an-Chip Designs for Security., , , , , , and . SoCC, page 248-253. IEEE, (2020)