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Disambiguation of "Okazaki, Shin'ichiro"

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A compact real-time vision system using integrated memory array processor architecture.

, , and . IEEE Trans. Circuits Syst. Video Techn., 5 (5): 446-452 (1995)

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Shin'ichiro Nakamura

 

Other publications of authors with the same name

A 3.84 gips integrated memory array processor., , , , and . Syst. Comput. Jpn., 27 (3): 26-36 (1996)Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2010)A low-cost mixed-mode parallel processor architecture for embedded systems., , , , and . ICS, page 253-262. ACM, (2007)An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems., , and . ISCA, page 134-145. IEEE Computer Society, (2005)IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements., , and . ICIP (3), page 294-297. IEEE, (2001)A real-time vision system using an integrated memory array processor prototype., , and . Mach. Vis. Appl., 7 (4): 220-228 (1994)A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications., , , and . IEICE Trans. Inf. Syst., 87-D (1): 136-145 (2004)An Integrated Memory Array Processor for Embedded Image Recognition Systems., , and . IEEE Trans. Computers, 56 (5): 622-634 (2007)Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications., , , , , , , and . IEEE J. Solid State Circuits, 30 (6): 637-643 (June 1995)A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements., , , and . IEEE J. Solid State Circuits, 38 (11): 1992-2000 (2003)