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s-class large-scale NW SoC using multiple FPGAs.

K. Terada, H. Uzawa, N. Ikeda, S. Shigematsu, N. Tanaka, and M. Urano. FPL, page 639-642. IEEE, (2012)

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Masami Th Nagatomo

Luise Masami Schmidt

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Extendable point-to-multi-point protocol processor for 10G-EPON MAC SoCs.N. Miura, A. Miyazaki, J. Kato, N. Tanaka, M. Urano, M. Nakanishi, and T. Shibata. ISCAS, page 1464-1467. IEEE, (2012)A reliable procedure in a new power management technique for a 200-Gbps packet forwarding LSI.S. Yasuda, S. Ohteru, Y. Itoh, K. Yamazaki, Y. Sekihara, T. Aoki, M. Urano, and T. Shibata. IEICE Electron. Express, 10 (11): 20130231 (2013)10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control.S. Yasuda, T. Hatano, H. Suto, M. Urano, M. Nakanishi, and T. Shibata. ISOCC, page 357-360. IEEE, (2011)A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table.Y. Kawamura, K. Imamura, N. Miura, M. Urano, S. Shigematsu, and Y. Matsuda. ISPACS, page 351-356. IEEE, (2015)A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function.K. Imamura, R. Honda, Y. Kawamura, N. Miura, M. Urano, S. Shigematsu, T. Matsumura, and Y. Matsuda. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (10): 2123-2134 (2017)A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON.S. Ohteru, T. Kawamura, H. Suto, M. Urano, M. Nakanishi, and T. Shibata. A-SSCC, page 305-308. IEEE, (2011)Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction.H. Uzawa, K. Terada, N. Ikeda, A. Miyazaki, M. Urano, and T. Shibata. GLOBECOM, page 1-5. IEEE, (2011)Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.K. Terada, H. Uzawa, N. Ikeda, S. Shigematsu, N. Tanaka, and M. Urano. FPL, page 639-642. IEEE, (2012)Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip.N. Miura, A. Miyazaki, J. Kato, N. Tanaka, S. Shigematsu, M. Urano, M. Nakanishi, and T. Shibata. IEICE Trans. Electron., 98-C (1): 45-52 (2015)

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Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.

Please choose a person to relate this publication to

Masami Th Nagatomo

Luise Masami Schmidt

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Urano, Masami"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.

Please choose a person to relate this publication to

Masami Th Nagatomo

Luise Masami Schmidt

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.