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Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication.

, , , and . VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 149-178. Springer, (2020)

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Methodologies for Modeling and Optimization of 2.5-D and 3-D Integration Architectures for Compute-In-Memory Applications.. Georgia Institute of Technology, Atlanta, GA, USA, (2023)base-search.net (ftgeorgiatech:oai:repository.gatech.edu:1853/72787).H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (10): 1592-1602 (October 2023)Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication., , , and . VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 149-178. Springer, (2020)Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance., , , , and . 3DIC, page 1-5. IEEE, (2021)A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect., , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 445-457 (2022)A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration., , , and . VLSI-SOC, page 159-164. IEEE, (2020)Electrical and Performance Benefits of Advanced Monolithic Cooling for 2.5D Heterogeneous ICs., , , and . 3DIC, page 1-5. IEEE, (2021)Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture., , , , , , , , , and 1 other author(s). ISLPED, page 1-6. IEEE, (2021)