Author of the publication

A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration.

, , , and . VLSI-SOC, page 159-164. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Design Space Exploration of Power Delivery For Advanced Packaging Technologies., , , , , and . CoRR, (2020)H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (10): 1592-1602 (October 2023)Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication., , , and . VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 149-178. Springer, (2020)3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation., , , , , , , and . CICC, page 663-670. IEEE, (2008)Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution., , and . SoCC, page 78-81. IEEE, (2004)Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation., , and . 3DIC, page 1-5. IEEE, (2014)Evaluation of 3DICs and fabrication of monolithic interlayer vias., , and . 3DIC, page 1-6. IEEE, (2013)Within-tier cooling and thermal isolation technologies for heterogeneous 3D ICs., , and . 3DIC, page 1-6. IEEE, (2013)Microfabrication, assembly, and hermetic packaging of mm-sized free-floating neural probes., , , , , , and . BioCAS, page 1-4. IEEE, (2017)High Density and Low-Temperature Interconnection Enabled by Mechanical Self-Alignment and Electroless Plating., , , and . 3DIC, page 1-4. IEEE, (2019)