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A networks-on-chip emulation/verification framework.

, , , , , , , and . Int. J. High Perform. Syst. Archit., 3 (1): 2-11 (2011)

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A software/hardware co-design methodology for embedded microprocessor core design., , and . IEEE Trans. Consumer Electronics, 45 (4): 1241-1246 (1999)An efficient protocol with synchronization accelerator for multi-processor embedded systems., , , , , , and . Parallel Comput., 39 (9): 461-474 (2013)A bus arbitration scheme for HDTV decoder SoC., , , and . APCCAS (2), page 79-83. IEEE, (2002)Embedded software optimization for MP3 decoder implemented on RISC core., , , and . IEEE Trans. Consumer Electronics, 50 (4): 1244-1249 (2004)Model-based coding for multiobject sequence., , and . VCIP, volume 4310 of Proceedings of SPIE, page 845-852. SPIE, (2001)Novel video signal processor with VLIW-controlled SIMD architecture., , and . VCIP, volume 4067 of Proceedings of SPIE, page 932-941. SPIE, (2000)A processor for MPEG decoder SOC: a software/hardware co-design approach., , , , and . Electronic Imaging: Image and Video Communications and Processing, volume 5685 of SPIE Proceedings, SPIE, (2005)An Estimation of Low Bound for Two-Dimensional Image Compression Coding., , , and . ICSC, volume 1024 of Lecture Notes in Computer Science, page 495-496. Springer, (1995)A networks-on-chip architecture design space exploration - The LIB., , , , , and . Comput. Electr. Eng., 35 (6): 817-836 (2009)An efficient scheduler of RTOS for multi/many-core system., , , , , and . Comput. Electr. Eng., 38 (3): 785-800 (2012)