( en | de | ru )

 

Disambiguation of "Lu, Shyue-Kung"

Author of the publication

copydeleteadd this publication to your clipboard
Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories.

, , , and . ATS, page 254-259. IEEE Computer Society, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Lu Lu

Zigmas Kungys

Hans Kungl

Angela Brigitte Kung

Erhard Küng

 

Other publications of authors with the same name

A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume., , , , and . ISCIT, page 1-5. IEEE, (2017)Efficient test and repair architectures for 3D TSV-based random access memories., , , and . VLSI-DAT, page 1-4. IEEE, (2013)Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs., , , and . VLSI-DAT, page 1-4. IEEE, (2015)Combinational circuit fault diagnosis using logic emulation., , , , and . ISCAS (5), page 549-552. IEEE, (2003)A built-in supply current test circuit for electrical interconnect tests of 3D ICs., , , and . 3DIC, page 1-6. IEEE, (2014)Yield enhancement techniques for 3-dimensional random access memories., , and . Microelectron. Reliab., 52 (6): 1065-1070 (2012)Fault-Aware Dependability Enhancement Techniques for Flash Memories., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (3): 634-645 (2020)Design-for-testability and fault-tolerant techniques for FFT processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (6): 732-741 (2005)A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs., , , , and . IEICE Trans. Inf. Syst., 101-D (8): 2053-2063 (2018)Defect Level Prediction Using Multi-Model Fault Coverage.. IEICE Trans. Inf. Syst., 87-D (6): 1488-1495 (2004)