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Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects.

, , , and . DAC, page 640-645. ACM, (2004)

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Microarchitecture Configurations and Floorplanning Co-Optimization., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 830-841 (2007)System level leakage reduction considering the interdependence of temperature and leakage., , and . DAC, page 12-17. ACM, (2004)Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects., , , and . DAC, page 640-645. ACM, (2004)Microarchitecture-level leakage reduction with data retention., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (11): 1324-1328 (2005)Temperature and supply Voltage aware performance and power modeling at microarchitecture level., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (7): 1042-1053 (2005)Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion., and . ICCAD, page 574-580. IEEE Computer Society / ACM, (2003)Microarchitecture Level Interconnect Modeling Considering Layout Optimization., and . J. Low Power Electron., 1 (3): 297-308 (2005)Hand Vein Recognition Based on Feature Coding., and . CCBR, volume 7701 of Lecture Notes in Computer Science, page 165-175. Springer, (2012)Scheduling of Soft Real-Time Systems for Context-Aware Applications., , , , and . DATE, page 318-323. IEEE Computer Society, (2005)Leakage power modeling and reduction with data retention., , and . ICCAD, page 714-719. ACM / IEEE Computer Society, (2002)