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SLOCOP-II: a versatile timing verification system for MOSVLSI.

, , , and . EURO-DAC, page 518-523. IEEE Computer Society, (1990)

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On the use of hierarchy in timing verification with statically sensitizable paths., , and . Great Lakes Symposium on VLSI, page 4-8. IEEE, (1992)Formal Hardware Verification in HOL and in Boyer-Moore: A Comparative Analysis., , , and . TPHOLs, page 340-347. IEEE Computer Society, (1991)SPI: an open interface integrating highly interactive electronic CAD tools., , , and . EURO-DAC, page 492-495. IEEE Computer Society, (1990)An Evaluation of Different Handwriting Observation Techniques from a Signature Verification Point of View., and . BSDIA, volume 1339 of Lecture Notes in Computer Science, page 273-282. Springer, (1997)On-line signature verification by dynamic time-warping., and . ICPR, page 38-42. IEEE Computer Society, (1996)A formal verification technique for embedded software., and . ICCD, page 352-357. IEEE Computer Society, (1996)CAD Tools for the optimized design of custom VLSI wave digital filters., , , , , , and . ICASSP, page 1465-1468. IEEE, (1985)Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment., , and . EURO-DAC, page 62-66. IEEE Computer Society, (1990)On the Comparison of HOL and Boyer-Moore for Formal Hardware Verification., , , and . Formal Methods Syst. Des., 2 (1): 45-72 (1993)A Parallel Method for Functional Verification of Medium and High Throughput DSP Synthesis., , and . ICCD, page 460-463. IEEE Computer Society, (1994)