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Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , и 2 other автор(ы). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 455-463 (2011)High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme., , , , , , , и . IEICE Trans. Inf. Syst., 93-D (1): 2-9 (2010)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , и . IEEE Des. Test Comput., 25 (2): 122-130 (2008)Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding., , и . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 942-953 (2017)Logic BIST Architecture for System-Level Test and Diagnosis., , , , , , , , , и 5 other автор(ы). Asian Test Symposium, стр. 21-26. IEEE Computer Society, (2009)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , и . Asian Test Symposium, стр. 19-24. IEEE Computer Society, (2013)Test compression and logic BIST at your fingertips., , , , и . ITC, стр. 2. IEEE Computer Society, (2005)Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard., , , , , , , , , и 6 other автор(ы). ITC, стр. 1-9. IEEE Computer Society, (2008)A circular pipeline processing based deterministic parallel test pattern generator., , , и . ITC, стр. 1-8. IEEE Computer Society, (2013)Test data compression based on clustered random access scan., , , , , , , , и . ATS, стр. 231-236. IEEE, (2006)