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Disambiguation of "Chen, Gengjie"

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FIT: Fill Insertion Considering Timing.

, , , , , , , and . DAC, page 221. ACM, (2019)

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Chen Chen

Chen Chen

Shih Chen Chen

Yi-Chen Chen

Chen-Loung Chen

 

Other publications of authors with the same name

Reproducible evaluation of Pan-Tilt-Zoom tracking., , , , and . ICIP, page 2055-2059. IEEE, (2015)Dim Sum: Light Clock Tree by Small Diameter Sum., and . DATE, page 174-179. IEEE, (2019)Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (9): 1902-1915 (2020)AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA., , , , and . CoRR, (2022)A two-step search engine for large scale boolean matching under NP3 equivalence., , , , and . ASP-DAC, page 592-598. IEEE, (2018)TreeNet: Deep Point Cloud Embedding for Routing Tree Construction., , , , and . ASP-DAC, page 164-169. ACM, (2021)SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm., , and . ICCAD, page 569-576. IEEE, (2017)Placement for Wafer-Scale Deep Learning Accelerator., , , , , and . ASP-DAC, page 665-670. ACM, (2021)RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs., , , , , , , , and . ICCAD, page 67. ACM, (2016)SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (6): 1217-1230 (2020)