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CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model., , , and . DAC, page 1-6. IEEE, (2020)Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems., and . ICCAD, page 1-8. ACM, (2019)Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration., , , , , , , , and . ICCAD, page 57:1-57:9. ACM, (2022)Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper)., , , , and . ICCAD, page 929-936. IEEE, (2017)TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction., , , , , , and . DATE, page 1-5. IEEE, (2023)Detailed routing by sparse grid graph and minimum-area-captured path search., , , , , and . ASP-DAC, page 754-760. ACM, (2019)A two-step search engine for large scale boolean matching under NP3 equivalence., , , , and . ASP-DAC, page 592-598. IEEE, (2018)Legalization algorithm for multiple-row height standard cell design., , and . DAC, page 83:1-83:6. ACM, (2016)Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment., , , and . ASP-DAC, page 176-182. ACM, (2021)RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs., , , , , , , , and . ICCAD, page 67. ACM, (2016)