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A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , и . ISSCC, стр. 464-465. IEEE, (2009)

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Shinichiro Nishizawa

Shinichiro Matsunaga

Shinichiro Kotsuka

 

Другие публикации лиц с тем же именем

Session 24 Overview: Advanced Embedded Memories Memory Subcommittee., , и . ISSCC, стр. 332-333. IEEE, (2021)Session 30 overview: Emerging memories: Memory and technology directions subcommittees., , , и . ISSCC, стр. 476-477. IEEE, (2018)A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode., , , , , , , , , и 5 other автор(ы). ISSCC, стр. 459-466. IEEE, (2006)A 32-Mb chain FeRAM with segment/stitch array architecture., , , , , , , , , и 9 other автор(ы). IEEE J. Solid State Circuits, 38 (11): 1911-1919 (2003)Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI., , , , , , и . IEICE Trans. Electron., 89-C (3): 263-270 (2006)A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode., , , , , , , , , и 5 other автор(ы). IEEE Trans. Very Large Scale Integr. Syst., 18 (12): 1745-1752 (2010)A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes., , , , , , , , , и 23 other автор(ы). ISSCC, стр. 464-465. IEEE, (2009)A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling., , , , , , , , , и 13 other автор(ы). IEEE J. Solid State Circuits, 41 (1): 54-62 (2006)SE1: What Technologies Will Shape the Future of Computing?, , , , , , , , , и . ISSCC, стр. 537-538. IEEE, (2021)Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs., , , , , и . IEEE J. Solid State Circuits, 50 (5): 1324-1331 (2015)