Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Hatsuda, Kosuke
add a person with the name Hatsuda, Kosuke
 

Other publications of authors with the same name

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance., , , , and . IEEE J. Solid State Circuits, 46 (2): 530-536 (2011)A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes., , , , , , , , , and 23 other author(s). IEEE J. Solid State Circuits, 45 (1): 142-152 (2010)A perspective on NVRAM technology for future computing system., , , , , and . VLSI-DAT, page 1-2. IEEE, (2019)Design of a 128-mb SOI DRAM using the floating body cell (FBC)., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 41 (1): 135-145 (2006)Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy Cells., , , , and . IEEE J. Solid State Circuits, 46 (9): 2148-2157 (2011)A 333MHz random cycle DRAM using the floating body cell., , and . CICC, page 259-262. IEEE, (2005)A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes., , , , , , , , , and 23 other author(s). ISSCC, page 464-465. IEEE, (2009)