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Formal Interpretation of Assertion-Based Features on AMS Designs., and . IEEE Des. Test, 32 (1): 9-17 (2015)The Notion of Cross Coverage in AMS Design Verification., , , , , and . ASP-DAC, page 217-222. IEEE, (2020)Counterexample Ranking Using Mined Invariants., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (12): 1978-1991 (2013)Feature Indented Assertions for Analog and Mixed-Signal Validation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (11): 1928-1941 (2016)Model checking on timed-event structures., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (5): 601-611 (2000)Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework., , , , and . ISED, page 267-271. IEEE, (2012)Formal methods for coverage analysis of architectural power states in power-managed designs., , , and . ASP-DAC, page 585-590. IEEE, (2012)Some results on Parametric Temporal Logic., , and . Inf. Process. Lett., 111 (20): 994-998 (2011)V_THR: An Adaptive Load Balancing Algorithm., , and . J. Parallel Distributed Comput., 42 (2): 101-108 (1997)Differential Fault Analysis Automation., , , and . IACR Cryptology ePrint Archive, (2017)