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Some results on Parametric Temporal Logic., , and . Inf. Process. Lett., 111 (20): 994-998 (2011)Instrumenting AMS assertion verification on commercial platforms., , , and . ACM Trans. Design Autom. Electr. Syst., 14 (2): 21:1-21:47 (2009)A static verification approach for architectural integration of mixed-signal integrated circuits., , , , and . Integr., 43 (1): 58-71 (2010)Model checking on timed-event structures., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (5): 601-611 (2000)Counterexample Ranking Using Mined Invariants., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (12): 1978-1991 (2013)Feature Indented Assertions for Analog and Mixed-Signal Validation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (11): 1928-1941 (2016)Adaptive Algorithms for Scheduling Static Task Graphs in Dynamic Distributed Systems., , and . HiPC, volume 1745 of Lecture Notes in Computer Science, page 143-150. Springer, (1999)Formal methods for coverage analysis of architectural power states in power-managed designs., , , and . ASP-DAC, page 585-590. IEEE, (2012)Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework., , , , and . ISED, page 267-271. IEEE, (2012)A SAT Based Verification Framework for Wireless LAN Security Policy Management Supported by STRBAC Model., , , and . CNSA, volume 89 of Communications in Computer and Information Science, page 232-241. Springer, (2010)