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Disambiguation of "Hanumolu, Pavan Kumar"

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3.2 A 0.0088mm2 Resistor-Based Temperature Sensor Achieving 92fJ·K2 FoM in 65nm CMOS.

, , , , and . ISSCC, page 60-62. IEEE, (2020)

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Pavan Kumar

Pavan Kumar

Pavan Kumar Penumakala

Pavan Kumar Pendli

Pavan Kumar Pamarthi

 

Other publications of authors with the same name

High-Performance CMOS TIA for Data Center Optical Interconnects., , , , , , and . BCICTS, page 9-16. IEEE, (2022)A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop., , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS., , , , and . ISSCC, page 272-273. IEEE, (2014)A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS., , , , , , and . ISSCC, page 152-154. IEEE, (2011)A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators., , , and . ISSCC, page 464-466. IEEE, (2012)A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4th-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS., , and . ISSCC, page 360-362. IEEE, (2012)A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer., , , , , , and . ISSCC, page 152-154. IEEE, (2012)10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS., , , and . ISSCC, page 1-3. IEEE, (2015)10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS., , , , and . ISSCC, page 192-193. IEEE, (2016)Jitter in high-speed serial and parallel links., , , , and . ISCAS (4), page 425-428. IEEE, (2004)