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Disambiguation of "Hanumolu, Pavan Kumar"

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High-Performance CMOS TIA for Data Center Optical Interconnects.

, , , , , , and . BCICTS, page 9-16. IEEE, (2022)

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Pavan Kumar

Pavan Kumar

Pavan Kumar Penumakala

Pavan Kumar Pendli

Pavan Kumar Pamarthi

 

Other publications of authors with the same name

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS., , , , , , , , and . VLSIC, page 352-. IEEE, (2015)23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS., , , , , , , , , and . ISSCC, page 398-399. IEEE, (2016)A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity., , , and . VLSIC, page 188-189. IEEE, (2012)10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS., , , , and . ISSCC, page 182-183. IEEE, (2017)A low spur fractional-N frequency synthesizer architecture., , , and . ISCAS (3), page 2807-2810. IEEE, (2005)A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC., , , , and . IEEE J. Solid State Circuits, 50 (4): 867-881 (2015)A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 53 (2): 445-457 (2018)Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques., , and . VLSI Design, page 20-21. IEEE Computer Society, (2012)Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation., , , , , , , and . ESSCIRC, page 25-28. IEEE, (2023)Area efficient phase calibration of a 1.6 GHz multiphase DLL., , and . CICC, page 1-4. IEEE, (2011)