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Disambiguation of "Coln, Michael C. W."

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"Split ADC" Calibration for All-Digital Correction of Time-Interleaved ADC Errors.

, , , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (5): 344-348 (2009)

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Hubert Cöln

Cornelia Cöln

Bernd Cöln

Rudolf Colnot

Thomas Colnot

 

Other publications of authors with the same name

A signal-independent background-calibrating 20b 1MS/S SAR ADC with 0.3ppm INL., , , , , and . ISSCC, page 242-244. IEEE, (2018)"Split ADC" Calibration for All-Digital Correction of Time-Interleaved ADC Errors., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (5): 344-348 (2009)Split ADC background self-calibration of a 16-b successive approximation ADC in 180nm CMOS., , , , and . I2MTC, page 310-313. IEEE, (2013)A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS., , , , , and . A-SSCC, page 153-156. IEEE, (2016)A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stability., , , , and . ISSCC, page 278-279. IEEE, (2013)Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC"., , , , and . IEEE J. Solid State Circuits, 41 (6): 1481 (2006)A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 53 (4): 1149-1160 (2018)Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results., , , , , and . IEEE J. Solid State Circuits, 53 (5): 1481-1492 (2018)Digital Background-Calibration Algorithm for "Split ADC" Architecture., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (2): 294-306 (2009)"Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC., , and . IEEE J. Solid State Circuits, 40 (12): 2437-2445 (2005)