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Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations., , , , , , , , , and 1 other author(s). ICCAD, page 209-216. IEEE, (2017)A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET., , , , , , , , , and 21 other author(s). A-SSCC, page 285-288. IEEE, (2018)A Methodology for Reusable Physical Design., , , , , , and . ISQED, page 243-249. IEEE, (2020)ACED: a hardware library for generating DSP systems., , , , , and . DAC, page 61:1-61:6. ACM, (2018)Unlocking Design Reuse with Hardware Compiler Frameworks.. University of California, Berkeley, USA, (2019)Flicker: a dynamically adaptive architecture for power limited multicore systems., , , and . ISCA, page 13-23. ACM, (2013)Hammer: a modular and reusable physical design flow tool: invited., , , , , , , , , and . DAC, page 1335-1338. ACM, (2022)A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance., , , , , , , , , and 21 other author(s). IEEE J. Solid State Circuits, 54 (10): 2786-2801 (2019)